Server memory decoded: RDIMM vs LRDIMM vs UDIMM

The one-line difference

Every DIMM sits between the CPU's memory controller and the DRAM chips. What changes between the types is whether there is a buffer in that path, and what it buffers.

Type	Buffer on the module	What it buffers	Where it is used
UDIMM (Unbuffered)	none	nothing — the controller drives the DRAM directly	desktops, laptops, entry/single-socket servers
ECC UDIMM	none	nothing (adds a dedicated ECC device)	entry servers and workstations
RDIMM (Registered)	RCD	command, address and clock	mainstream server memory
LRDIMM (Load-Reduced)	RCD plus data buffers	command, address, clock and data	maximum-capacity server memory (chiefly DDR4-era)

The register and the data buffer

RCD (Registering Clock Driver). On an RDIMM, a small chip re-drives the command, address and clock signals one cycle before they reach the DRAM. This reduces the load on the CPU's memory controller and limits the impact on signal integrity. The payoff is that a channel can carry more chips and more ranks while staying reliable — exactly what a 16- or 32-slot server needs.

Data buffers. An LRDIMM keeps the RCD and adds buffers on the data lines as well, isolating the DRAM's data pins from the bus. Because the controller now sees a handful of buffers instead of every DRAM device, the electrical load barely rises as ranks are added. On DDR4 this made LRDIMM the route to the very highest-capacity modules. On DDR5, however, the largest capacities are reached with 3DS RDIMMs rather than LRDIMM, and many DDR5 server platforms are RDIMM-only, so treat "LRDIMM for maximum capacity" as a DDR4-era rule.

UDIMM has neither. The controller talks to the DRAM directly. This is simple and low-latency, but it limits how many chips, ranks and modules a channel can carry — fine for a two-to-four-slot desktop, not for a densely populated server.

ECC — the feature that defines server memory

ECC (Error-Correcting Code) lets a system detect and correct memory bit errors instead of silently corrupting data or crashing. It is standard on server memory, and on DDR5 it exists in two distinct layers:

• Side-band (link) ECC — extra DRAM devices carry check bits across the bus. DDR4 uses a 72-bit channel (64 data + 8 ECC). DDR5 uses two independent sub-channels per module, each 32 data + 8 ECC bits — 64 data + 16 ECC in total. This is the ECC the memory controller uses to correct errors in flight.
• On-die ECC (DDR5 only) — every DDR5 die, including consumer non-ECC UDIMMs, corrects single-bit errors inside the chip, a response to how tightly DDR5 packs its cells. Crucially, on-die ECC protects only the data on the die, not data in transit between the module and the CPU. It is not a substitute for true side-band server ECC.

UDIMMs come in non-ECC (desktop) and ECC UDIMM (entry-server / workstation) variants. RDIMMs and LRDIMMs are ECC by definition.

The four types side by side

	UDIMM	ECC UDIMM	RDIMM	LRDIMM
Buffering	none	none	command/address/clock	command/address/clock + data
Side-band ECC	no	yes	yes	yes
Relative capacity per module	lowest	low	high	highest
Ranks typically supported	1R–2R	1R–2R	1R–4R (8R with 3DS)	4R–8R
Signal integrity under many ranks	limited	limited	strong	strongest
Typical role	consumer	entry server / workstation	mainstream server	max-capacity server

Ranks, x4/x8 and 3DS — where capacity comes from

• Rank. A rank is a full data-width (64-bit, or 72/80-bit with ECC) set of DRAM chips the controller addresses at once. Modules are 1R (single), 2R (dual), 4R (quad) or 8R (octal) rank. More ranks mean more capacity and better rank interleaving, but more load on the channel — which is precisely why registered and load-reduced buffering exist.
• x4 vs x8. This is the width of each DRAM device. x8 modules use fewer, 8-bit-wide chips; x4 modules use more, 4-bit-wide chips and enable stronger, device-level error correction (single-device-data-correction, the Chipkill class of protection). Server platforms generally forbid mixing x4 and x8 within a socket.
• 3DS (3-Dimensional Stacking). TSV (through-silicon-via) stacking bonds several DRAM dies into one package and presents them as extra ranks. 3DS RDIMMs and LRDIMMs are how the largest modules are built — for example HPE's 128 GB 4-rank and 256 GB 8-rank 3DS RDIMMs.

You don't pick the type — the platform does

This is the point that saves buyers the most grief: the CPU and server define which module types, speeds, ranks and capacities are supported. You match the module to the platform, never the other way round. Most recent Xeon and EPYC servers are RDIMM-only.

• RDIMM and LRDIMM cannot be mixed in one system. HPE halts the machine with an "unsupported DIMM configuration" message stating the system can hold only one DIMM type at a time (HPE server memory population rules, document a50007437enw).
• DDR5 UDIMMs and RDIMMs are keyed differently and are not pin-compatible — you cannot force one into the other's slot.
• Rank mixing within a channel is generally disallowed, with narrow, documented exceptions (for instance, HPE permits a 2-rank + 1-rank pair only when all 16 slots per socket are populated).
• No x4/x8 mixing across a socket.

Buyer's checklist

• Check the server's qualified vendor list (QVL) for module type (RDIMM vs LRDIMM), speed, rank and capacity — this is not negotiable.
• Do not mix RDIMM and LRDIMM, and do not mix x4 with x8 across a socket.
• For maximum capacity per socket, look for 3DS RDIMM/LRDIMM; for mainstream builds, standard RDIMM is the norm.
• Remember that all ECC server memory protects data in flight; DDR5's on-die ECC is an addition, not server-grade protection on its own.

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