DDR4 vs DDR5 for servers, and how to populate
DDR5 is now the default for new servers, but a great deal of capable, cost-effective kit — especially in the refurbished market — is DDR4. The generation sets the headline numbers; the population rules decide how much of that performance you actually keep. This guide compares the two, then shows how to fill the slots so a server runs at full speed.
DDR4 vs DDR5 at a glance
| DDR4 | DDR5 | |
|---|---|---|
| Server data rates | 2133–3200 MT/s (server platforms) | 4800–6400 MT/s (server-qualified) |
| Supply voltage (VDD) | 1.2 V | 1.1 V |
| Voltage regulation (PMIC) | on the motherboard | on the DIMM |
| Channel architecture | one 72-bit channel (64 data + 8 ECC) | two independent sub-channels per DIMM (32 data + 8 ECC each) |
| Burst length | BL8 | BL16 |
| Bank groups / banks | baseline | 2x bank groups, 2x banks |
| Max die density (JEDEC) | 16 Gb | 64 Gb |
| On-die ECC | no | yes (on every DDR5 die) |
| Signal equalisation | — | Decision Feedback Equalisation |
DDR5 launched at 4800 MT/s, and JEDEC's original DDR5 standard topped out at 6400 MT/s — but the standard has since been extended: the JESD79-5C update of April 2024 raised the defined ceiling to 8800 MT/s (DDR5-8800). Server-qualified registered DDR5, however, currently tops out around 6400 MT/s, against DDR4's official ceiling of 3200 MT/s. DRAM makers rate individual dies higher still, yet a server runs only the JEDEC data rate its CPU qualifies — no more.
Channels per socket — where server bandwidth comes from
Each memory channel is a parallel path; more channels means more aggregate bandwidth. This is the single biggest architectural difference between server and desktop memory, and it grew with DDR5.
| CPU family | Memory | Channels per socket |
|---|---|---|
| Intel Xeon Scalable (Skylake / Cascade Lake) | DDR4 | 6 |
| Intel Xeon (Ice Lake, 3rd Gen) | DDR4 | 8 |
| Intel Xeon (4th / 5th Gen, Sapphire / Emerald Rapids) | DDR5 | 8 |
| AMD EPYC (Rome / Milan) | DDR4 | 8 |
| AMD EPYC (Genoa / Turin, 9004 / 9005) | DDR5 | 12 |
On a 4th Gen Xeon, HPE describes four memory controllers per CPU, each driving two of the eight channels. The practical implication is stark: a 12-channel EPYC needs twelve DIMMs per socket to reach full bandwidth, so a half-populated server leaves a large fraction of its memory performance unused.
Ranks in one paragraph
Modules are single-rank (1R), dual-rank (2R), quad-rank (4R) or octal-rank (8R), built from x4 or x8 DRAM devices. At the same capacity, dual-rank often out-performs single-rank because the controller can interleave accesses across ranks — but every extra rank adds electrical load, which is why higher-rank and higher-capacity modules rely on registered (RDIMM) or load-reduced (LRDIMM) buffering, and why they can force a lower bus speed when you fill both slots on a channel.
1DPC vs 2DPC — the speed you trade for capacity
Many server channels have two slots. Filling both — two DIMMs per channel (2DPC) — adds capacity, but the bus slows down because the controller is now driving twice the load. As a rule, 2DPC costs one or two speed grades.
| Platform (example) | 1 DIMM per channel | 2 DIMMs per channel |
|---|---|---|
| 4th Gen Intel Xeon (HPE Gen11 / Dell R660) | DDR5-4800 | DDR5-4400 |
| 5th Gen Intel Xeon | DDR5-5600 | one to two grades lower |
| AMD EPYC 9005 (Turin) | DDR5-6400 | one to two grades lower |
A further wrinkle on EPYC: some modules marketed at 6400 MT/s are only supported up to 6000 MT/s in certain configurations, so always read the platform's qualified speed rather than the sticker.
Takeaway: to hit the highest data rate, use one larger DIMM per channel (1DPC) rather than two smaller ones. Choose 2DPC only when the extra capacity matters more than the last speed grade.
Balanced population — the rule that actually matters
The most common — and most expensive — mistake is an unbalanced configuration. Servers reach peak bandwidth by interleaving reads across all channels; if the channels are not populated identically, the interleave region shrinks and throughput falls. HPE publishes the effect for an 8-channel Xeon, measured against a full 8-channel interleave (HPE server memory population rules, document a50007437enw):
| DIMMs per CPU | Channels interleaved | Throughput vs peak |
|---|---|---|
| 1 | 1 | 12.5% |
| 2 | 2 | 25% |
| 4 | 4 | 50% |
| 6 | 6 | 75% |
| 8 | 8 | 100% |
| 12 | 8 + 4 | 100% in one region, 50% in the other |
| 16 | 8 + 8 | 100% |
Note the 12-DIMM trap on an 8-channel CPU: it looks like "more memory," but half of it interleaves across only four channels, so real-world throughput swings between peak and 50% of peak depending on where data lands. The clean populations are 8 or 16 DIMMs on an 8-channel Xeon, and 12 or 24 on a 12-channel EPYC.
Rules of thumb:
- Populate every channel of each installed CPU identically.
- Split memory evenly across sockets — an imbalance forces slow cross-socket (NUMA) access for the busier CPU.
- Fill the first (white) slot of each channel before the second (black), in the documented order.
- Mixed-speed DIMMs run at the lowest common speed; mixed types may refuse to boot.
JEDEC vs XMP / EXPO — servers run JEDEC
XMP (Intel) and EXPO (AMD) are consumer overclocking profiles that push desktop memory past its JEDEC-rated speed. Server memory does the opposite. It runs strict JEDEC profiles that "just work," because in a server, stability and data integrity outrank a handful of extra megatransfers. Registered ECC memory on Xeon and EPYC platforms follows server-grade JEDEC data rates, and OEM firmware generally does not expose XMP/EXPO on RDIMM/LRDIMM. If a module is advertised with an XMP or EXPO speed and aggressively tight timings, it is a consumer part — not server memory.
A note on Intel Optane persistent memory
You may still see Intel Optane persistent memory (PMem) listed against older servers. It only ever existed for DDR4-era Xeon — 2nd Gen (Cascade Lake) and 3rd Gen (Ice Lake) Scalable processors. Intel wound down the Optane business in 2022, and no DDR5-generation Optane PMem shipped: the DDR5-era successor — the 300-series, code-named "Crow Pass" — was slated for Sapphire Rapids but cancelled in January 2023, before any commercial release. On DDR5 platforms, large-capacity and memory-tiering needs are met with high-capacity 3DS RDIMMs and, increasingly, CXL-attached memory — not Optane. In practice, an Optane requirement is a reliable signal that the platform is DDR4-generation.
Populate-it-right checklist
- Match the DDR generation, module type and speed to the CPU's qualified list.
- Populate every channel; balance across channels and across sockets.
- On an 8-channel CPU, prefer 8 or 16 DIMMs; on a 12-channel EPYC, prefer 12 or 24.
- Use 1DPC with larger modules for top speed; move to 2DPC only when capacity wins.
- Do not mix module types, and use matched kits to avoid the lowest-common-speed penalty.
- Ignore XMP/EXPO — server memory runs JEDEC.
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