AMD EPYC decoded: Naples to Turin and reading a SKU
AMD EPYC uses a tighter numbering scheme than Intel: four digits, no metal tiers, and — helpfully — a single digit that tells you the generation and another that tracks the core count. There is one wrinkle: AMD changed the leading digit when it moved socket, so there are effectively two schemes to know. Learn both and you can read any EPYC from the 2017 Naples launch to the current Turin line at a glance. This is the reference for doing exactly that.
How to read an EPYC part number
Scheme A — the 7000 series (Naples, Rome, Milan)
The first three generations all begin with 7. Take EPYC 7742:
| Position | In "7742" | What it tells you |
|---|---|---|
| 1st digit | 7 | Series identifier |
| 2nd–3rd digits | 74 | Model / relative performance within the generation (higher = more capable) |
| 4th digit | 2 | Generation: 1 = Naples (Zen), 2 = Rome (Zen 2), 3 = Milan (Zen 3) |
| Suffix (optional) | — | P, F, X or H (see below) |
So 7742 is a 2nd-Generation "Rome" part — and per AMD's datasheet it is a 64-core, 128-thread chip with 256 MB of L3 cache, 128 lanes of PCIe 4.0 and a 225 W TDP.
Scheme B — the 9000 / 8000 series (Genoa, Bergamo, Siena, Turin)
With the move to Socket SP5 in 2022 AMD switched the leading digit. Take EPYC 9654 and EPYC 9965:
| Position | In "9654" / "9965" | What it tells you |
|---|---|---|
| 1st digit | 9 | Platform family: 9 = 9000-series (Socket SP5, mainstream / HPC / cloud); 8 = 8000-series (Socket SP6, single-socket edge / telco — "Siena") |
| 2nd digit | 6 / 9 | Core-count tier (see mapping below) |
| 3rd digit | 5 / 6 | Further model differentiation |
| 4th digit | 4 / 5 | Generation: 4 = Zen 4 (Genoa / Bergamo), 5 = Zen 5 (Turin) |
| Suffix (optional) | — | P, F or X |
The second digit is a genuinely useful shortcut to core count. Read straight off the 5th-Gen "Turin" datasheet, it maps like this:
| 2nd digit | Cores per socket (Turin, 9005) | Example |
|---|---|---|
| 0 | 8 | 9015 |
| 1 | 16 | 9115 / 9135 / 9175F |
| 2 | 24 | 9255 / 9275F |
| 3 | 32–36 | 9335 / 9355 / 9365 / 9375F |
| 4 | 48 | 9455 / 9475F |
| 5 | 64–72 | 9535 / 9555 / 9565 / 9575F |
| 6 | 96 | 9645 / 9655 |
| 7 | 128 | 9745 / 9755 |
| 8 | 160 | 9845 |
| 9 | 192 | 9965 |
Treat the mapping as a tier, not a formula — the exact figure shifts slightly between the 9004 and 9005 generations, so confirm the core count on the datasheet. (In the 4th-Gen line, for instance, digit 5 is 64 cores and digit 6 covers 84–96.)
The five generations at a glance
Every figure below is from AMD's own series datasheet (or, for Naples, the AMD product page).
| Gen | Series | Code name | Core arch. | Launch | Socket | Max cores / socket | Memory | Max PCIe / socket |
|---|---|---|---|---|---|---|---|---|
| 1st | 7001 | Naples | Zen | 2017 | SP3 | 32 (7601) | 8-ch DDR4 | PCIe 3.0, 128 lanes |
| 2nd | 7002 | Rome | Zen 2 | 2019 | SP3 | 64 (7742) | 8-ch DDR4-3200 | PCIe 4.0, 128 lanes |
| 3rd | 7003 | Milan / Milan-X | Zen 3 | 2021 | SP3 | 64 (7763) | 8-ch DDR4-3200 | PCIe 4.0, 128 lanes |
| 4th | 9004 / 8004 | Genoa, Genoa-X, Bergamo, Siena | Zen 4 / Zen 4c | 2022–23 | SP5 (Siena: SP6) | 96 Genoa (9654); 128 Bergamo (9754) | 12-ch DDR5-4800 | PCIe 5.0, 128 lanes |
| 5th | 9005 | Turin / Turin Dense | Zen 5 / Zen 5c | 2024 | SP5 | 128 Zen 5 (9755); 192 Zen 5c (9965) | 12-ch DDR5-6400 | PCIe 5.0, 128 lanes (up to 160 in a 2-socket server) |
A few architectural notes that shape a purchase:
- EPYC has offered 128 PCIe lanes per socket since Naples in 2017 — a consistent strength for GPU- and NVMe-dense servers.
- Cache scales dramatically at the top. Milan reaches 256 MB of L3; Genoa 384 MB; and the 3D V-Cache parts go further still — the Genoa-X 9684X carries 1,152 MB of L3, while Turin's Zen 5 flagship 9755 holds 512 MB.
- "Bergamo" and "Turin Dense" use the compact Zen 4c / Zen 5c cores to pack the highest core counts (128 and 192 respectively) for cloud-native, scale-out density.
Suffix letters
| Suffix | Meaning | Example |
|---|---|---|
| (none) | Standard part, supports one- and two-socket servers | 9654, 7763 |
| P | Single-socket only — same cores, frequency and cache as the non-P part, positioned for 1P builds | 9654P, 7713P |
| F | High-frequency — fewer cores at the highest clocks, for per-core-limited (and per-core-licensed) workloads | 9575F, 9374F, 7F72 |
| X | 3D V-Cache — a very large L3 for cache-bound HPC, EDA and technical computing | 9684X, 9384X |
The X line began with the 3rd-Gen "Milan-X" parts (the first EPYC with 3D V-Cache) and continued as "Genoa-X". The 8004 "Siena" line is a separate branch: single-socket, lower-power parts on Socket SP6 aimed at the edge and telco.
Sockets and drop-in upgrades
- Socket SP3 carries Naples, Rome and Milan. Rome and Milan are drop-in on an SP3 board with a firmware update — so a Rome → Milan CPU swap is a cheap capacity bump on hardware you already own. (Naples-era boards may need a newer revision for Rome.)
- Socket SP5 carries Genoa, Genoa-X, Bergamo and Turin — meaning a Turin chip can drop into a Genoa-generation board with a BIOS update.
- Socket SP6 carries Siena (8004).
Buying in South Africa: refurb versus new
- The refurbished EPYC volume is Rome (7002) and Milan (7003) on Socket SP3. A Rome-to-Milan upgrade on the same board is one of the best-value capacity bumps in the second-hand market. Naples (7001) is largely end-of-life.
- The new-build tier is Genoa, Bergamo and Turin on SP5 — the parts to specify when you need DDR5 bandwidth, PCIe 5.0 and the highest core density.
- Pick the suffix for the job. F-series parts are the ones to weigh when per-core software licences dominate cost (fewer, faster cores); X-series for cache-bound HPC and EDA; P to save on single-socket builds.
- Cost the licences before the cores. A 192-core Turin is a virtualisation powerhouse, but VMware, Windows Server and SQL Server all charge per physical core — see our Xeon-versus-EPYC guide for the maths.
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